Late Design Changes (ECOs) for Sequentially Optimized Esterel Designs

Late Design Changes (ECOs) for Sequentially Optimized High-Level Esterel Designs

Late changes in silicon design, called ECO, is a common although undesired practice. They happen due to last minute changes in the specifications or to design bugs found at the late stage, sometimes after the tapeout. At this stages going through the topdown design flow is infeasible, because it would take too long and lead to undesirably large perturbations to the physical layout. High-level d...

Reusing Verilog Designs in the Synchronous Language Esterel

Veriest is an automatic translator that converts synthesizable Verilog designs into the synchronous language Esterel. The translation into a synchronous language can expose hidden flaws in the original design, including subtle race conditions. In addition, the extensive libraries of verified Verilog designs can now be reused in synchronous designs. Verilog and Esterel have different models and ...

Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study

The design of control units of modern processors is quite complex due to many speed-up techniques like pipelining and out-of-order execution. The existing approaches to formal veriication of processor designs are applicable to very high level descriptions that ignore timing details of control signals. In this paper, we propose an approach for veriication of detailed design of processors. Our ap...

Model Checking CTL[DC] properties of SMV, Verilog and Esterel Designs

Constructive Analysis of Cyclic Circuits ( EDTC , Paris , March 1996 )

Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard...